1. Field of the Invention
The present invention relates to a semiconductor device, having a vertical double diffused metal oxide semiconductor transistor having a trench gate structure, and a method for manufacturing the same.
2. Description of Related Art
A trench gate structure is generally known as an effective structure for refining a vertical double diffused metal oxide semiconductor field effect transistor (VDMOSFET).
FIG. 5 is a schematic sectional view of a conventional semiconductor device including a trench gate VDMOSFET.
A semiconductor device 101 includes an N+ (high concentration N) substrate 102. An N− (low concentration N) epitaxial layer 103 is laminated onto the N+ substrate 102. A base layer portion of the N− epitaxial layer 103 is an N− region 104, and at a top layer portion of the N− epitaxial layer 103, a P− body region 105 is formed vertically adjacent to the N− region 104.
A trench 106 is formed by digging in from a top surface of the N− epitaxial layer 103. The trench 106 penetrates through the P− body region 105, and a deepest portion thereof reaches the N− region 104. Inside the trench 106, a gate insulating film 107 made of SiO2 (silicon oxide) is formed so as to cover an inner surface thereof. A gate electrode 108 made of a polysilicon (doped polysilicon) doped with a high concentration of an N impurity is embedded at an inner side of the gate insulating film 107.
On top layer portions of the P− body region 105, N+ source regions 109 are formed along the trench 106. Further, on top layer portions of the P− body region 105, P+ body contact regions 110 are formed so as to penetrate through the N+ source regions 109.
An interlayer insulating film 113 is laminated onto the N− epitaxial layer 103. A gate wiring 114 is formed on the interlayer insulating film 113. The gate wiring 114 is contacted (electrically connected) to the gate electrode 108 via a contact hole 115 formed in the interlayer insulating film 113. A source wiring 116 is electrically connected to the N+ source regions 109 and the body contact regions 110 via contact holes (not shown) formed in the interlayer insulating film 113.
A drain electrode 117 is formed on a rear surface of the N+ substrate 102.
In a process of manufacturing the semiconductor device 101, a silicon oxide film is formed on the top surface of the N− epitaxial layer 103, including the inner surface of the trench 106, and a deposition layer of the doped polysilicon is formed on the silicon oxide film. The doped polysilicon deposition layer fills the interior of the trench 106 completely and is formed to a thickness covering the silicon oxide film outside the trench 106. Thereafter, by etch back, the portion of the doped polysilicon deposition layer present outside the trench 106 is removed, and the gate electrode 108 made of the doped polysilicon is formed inside the trench 106.
After the gate electrode 108 is thus formed, a cleaning process for cleaning the top surface of the N− epitaxial layer 103 is performed before ion implantation for forming the N+ source regions 109. In this cleaning process, first, HF (hydrofluoric acid) is supplied to the silicon oxide film exposed by etch back of the doped polysilicon, and the portion of the silicon oxide film outside the trench 106 is removed. Then, by a thermal oxidation process, a sacrificial oxide film is formed on a top surface of the gate electrode 108 and the top surface of the N− epitaxial layer 103. HF is then supplied to the sacrificial oxide film, and the sacrificial oxide film is removed by the HF.
After the cleaning process, the N+ source regions 109 and the body contact regions 110 are formed. Thereafter, by a CVD method, the interlayer insulating film 113 of a predetermined thickness is formed on the N− epitaxial layer 103. The contact hole 115 is then formed in the interlayer insulating film 113 by photolithography and etching.
However, the doped polysilicon is more readily oxidized (for example, is about three times in oxidation rate) compared to silicon that is not doped with an impurity. Thus, in the cleaning process, the sacrificial oxide film that is thicker than the oxide film formed on the top surface of the N− epitaxial layer 103 is formed on the top surface of the gate electrode 108. Thus, after removal of the sacrificial oxide film, the top surface of the gate electrode 108 becomes lower than the top surface of the N− epitaxial layer 103. That is, in the cleaning process, the gate electrode 108 develops a greater film thickness loss than the N− epitaxial layer 103.
Such film thickness loss of the gate electrode 108 causes variation of height (depth) among gate electrodes 108 (among a plurality of gate electrodes 108 formed on the semiconductor device 101 and/or among respective gate electrodes 108 of a plurality of semiconductor devices 101). Variation of height among gate electrodes 108 may cause variation of transistor characteristics. Further, when the top surface of the gate electrode 108 becomes excessively lower than the top surfaces of the N+ source regions 109 (N− epitaxial layer 103), desired transistor characteristics may not be exhibited.
Still further, when the top surface of the gate electrode 108 becomes lower than the top surface of the N− epitaxial layer 103, the interlayer insulating film 113 partially increases in thickness on the gate electrode 108. Thus, when the contact hole 115 for contact with the gate electrode 108 and the contact holes for contact with the N+ source regions 109 are formed simultaneously in the interlayer insulating film 113, the contact hole 115 may not penetrate through the interlayer insulating film 113 as shown in FIG. 5 and a contact failure may be caused between the gate electrode 108 and the gate wiring 114.
Yet further, during forming of the gate electrode 108, the doped polysilicon deposition layer grows from the top surface of the N− epitaxial layer 103 including the inner surface of the trench 106. On the surface of the doped polysilicon deposition layer, a recess recessed toward the trench 106 is thus formed at a position opposing to the trench 106. As etch back of the doped polysilicon deposition layer progresses, the recess in the top surface of the doped silicon deposition layer increases, and a recess is finally left in the top surface of the gate electrode 108. Due to both the recess and the film thickness loss of the gate electrode 108 during the cleaning process, when the thickness of the portion of the interlayer insulating film 113 on the gate electrode 108 increases more, it is more likely to cause a contact failure between the gate electrode 108 and the gate wiring 114.